A conventional integrated circuit contains a plurality of patterns of metal lines separated by inter-wiring spacings and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the metal patterns of vertically spaced metallization layers are electrically interconnected by vias. Metal lines formed in trench-like openings typically extend substantially parallel to the semiconductor substrate. Semiconductor devices of such type, according to current technology, may comprise eight or more levels of metallization to satisfy device geometry and micro-miniaturization requirements.
A common method for forming metal lines or plugs is known as “damascene.” Generally, this process involves forming an opening in the dielectric interlayer, which separates the vertically spaced metallization layers. The opening is typically formed using conventional lithographic and etching techniques. After an opening is formed, the opening is filled with copper or copper alloys to form a via. Excess metal material on the surface of the dielectric interlayer is then removed by chemical mechanical planarization (CMP).
Copper has replaced aluminum because of its lower resistivity. However, copper still suffers from electro migration (EM) and stress migration (SM) reliability issues as geometries continue to shrink and current densities increase.
FIG. 1 illustrates a cross-sectional view of a conventional interconnection structure 1 formed using damascene processes. Metal lines 2 and 4, which are typically formed of copper or copper alloys, are interconnected by via 10. Inter-metal-dielectric (IMD) 8 separates the two layers where metal lines 2 and 4 are located. Etch stop layer (ESL) 5 is formed on lower layer copper line 2. Diffusion barrier layers 12 and 14 are formed to prevent copper from diffusing into surrounding materials. The interconnection structure 1 illustrated in FIG. 1 suffers from electro-migration and stress-migration problems. Since the copper line 2 is in direct contact with a dielectric ESL 5, the character difference between copper 2 and dielectric ESL 5 causes higher electro-migration and stress migration, and thus device reliability is degraded. In addition, ESL 5 typically has a higher dielectric constant (k value) than low-k dielectric layers 6 and 8. As a result, the parasitic capacitances between the metal lines are increased.
FIG. 2 illustrates an improved interconnection structure 3. A metal cap layer 16 is formed on copper line 2. Cap layer 16 is typically formed of materials suffering less from electro migration and stress migration. This layer improves the reliability of the interconnect structure by reducing copper surface migration. It has been found that under stressed conditions, the mean time to failure (MTTF) of the interconnect structure 3 is ten times longer than that of the interconnection structure 1. With the cap layer 16, the stress-induced void formation is also significantly reduced. Additionally, the parasitic capacitances are also reduced.
However, the introduction of cap layer 16 generates another problem. Cap layer 16 may be degraded by oxygen or chemical contamination. This not only introduces voids into cap layer 16 and increases the surface roughness, but it also increases the resistance of the via structure. A more severe problem is that the probability of via failure increases. Therefore, in order to improve the quality of the interconnect structures, a new interconnect structure and a method for forming the same are needed.